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Physical parametric analysis of 16nm n-channel Carbon-Nanotube transistors for manufacturability

Physical parametric analysis of 16nm n-channel Carbon-Nanotube transistors for manufacturability,10.1109/ICM.2010.5696141,Yanan Sun,Volkan Kursun

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Physical parametric analysis of 16nm n-channel Carbon-Nanotube transistors for manufacturability   (Citations: 2)
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Carbon-Nanotube MOSFET (CN-MOSFET) is a promising future device candidate. The electrical characteristics of 16nm N-type CN-MOSFETs are explored in this paper. The optimum high-speed N-type CN-MOSFET device profiles with different number of tubes are identified for achieving the highest on-state to off-state current ratio (Ion/Ioff) with a high substrate (bottom gate) bias voltage. Technology development guidelines for achieving high-speed, area efficient, and manufacturable integrated circuits are provided.
Conference: International Conference on Microelectronics - ICM , 2010
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    • ...Analysis and optimization of n-channel CN-MOSFETs are presented in [5]...
    • ...The full set of physical parameters of 16nm n-channel CN-MOSFETs is presented in [5]...
    • ...The channel of a CN-MOSFET is composed of an array of multiple nanotubes to be able to produce sufficient current as illustrated in Fig. 1. The strength of a CN-MOSFET can be adjusted by the number of tubes (N) [5]...
    • ...The current produced by a CN-MOSFET depends on important physical parameters such as the diameters of nanotubes, the inter-tube pitch, and the number of tubes [5]...
    • ...2 and 3. When the substrate is connected to 0V (Vsub = 0V), enlarging the CN diameter enhances both Ion and Ioff for a fixed number of tubes and a fixed pitch as shown in Fig. 2. Ion is enhanced with the increased diameter due to the reduction of the resistances of channel, source, and drain areas [5]...
    • ...Ioff is determined by the energy bandgap (Eg) of nanotubes and the band-to-band tunneling current (Ibtbt) in a CN-MOSFET [5], [7]...
    • ...When the substrate voltage is increased from 0V (connected to ground) to 0.7V (connected to the power supply [5]), Ion is enhanced by stronger channel inversion...
    • ...achievable Ion/Ioff is enhanced by up to 43% as compared to the maximum Ion/Ioff values reported in [5] for various transistor sizes...
    • ...A shorter pitch is desirable to enhance the integration density of a chip with CN-MOSFET technology [5]...
    • ...The optimum nanotube diameters are insensitive to the scaling of array pitch as discussed in [5]...
    • ...Similar to the optimization study presented in [5], 5%, 10%, 15%, and 20% degradations from the ideal maximum Ion/Ioff (that could only be achieved at impractically large pitches) are assumed to be acceptable for implementing high performance and compact integrated circuits in this section...
    • ...Shortening the pitch for smaller device area degrades Ion/Ioff as listed in Table 1. There is therefore a tradeoff between switch performance (determined by Ion/Ioff) and area (determined by Wg) in nanotube array pitch selection [5]...
    • ...For low-cost and high-yield manufacturability, it is highly desirable to have only one uniform nanotube diameter for a single-Vth CN-MOSFET technology across a chip [5]...

    Yanan Sun, et al. Leakage current and bottom gate voltage considerations in developing m...

    • ...CN-MOSFETs for achieving high-speed operation are presented in [1] and [2], respectively...
    • ...The strength of a CN-MOSFET is typically adjusted by varying the number of tubes (N) [1], [2]...
    • ...W g is typically determined by the overhang width, the pitch, and the number of tubes in a CN-MOSFET [1], [2]...
    • ...Similar to the optimization studies presented in [1], [2], and [9], 5%, lO%, 15%, and 20% degradations from the ideal maximum IonlIoff (that could only be achieved at impractically large pitches) are assumed to be acceptable for implementing high performance and compact integrated circuits in this section...
    • ...Shortening the pitch for smaller device area degrades IonlIoff as listed in Table 1. There is therefore a tradeoff between switch performance and CN-MOSFET integration density in nanotube array pitch selection [1], [2] ...

    Yanan Sun, et al. Substrate bias considerations for low leakage 16nm p-channel carbon na...

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